A conventional control scheme for switching regulators is pulse-width modulation (PWM). PWM control uses a constant switching frequency, but varies the duty cycle as the load current varies. This scheme generally achieves good regulation, low noise spectrum, and high power efficiency. However, when the load current is low the PWM mode is known to be inefficient due to primarily switching loss and high quiescent current. It is known that by adjusting the switching frequency according to the load current, the power efficiency at light load can be improved.
In one improved arrangement, the converter normally operates in continuous-conduction-mode (CCM), and automatically enters discontinuous conduction mode (DCM) at low load for optimum efficiency. DCM is also known as pulse frequency modulation (PFM) or Diode Emulation Mode (DEM). In CCM the converter operates as a synchronous rectifier. In DEM the low-side MOSFET stays off, blocking negative current flow from the output inductor.
FIG. 1 shows operation under DCM for load currents up to I_Critical (referred to herein as low load conditions), and CCM for load currents at or above I_Critical (referred to herein as heavy load conditions). Under CCM the converter operates with a constant duty cycle (D). Under DCM, the duty cycle is adjusted according to the load current.
For linear control schemes, the duty cycle is determined by the error amplifier output voltage VCOMP. As noted above, for CCM operation, the duty cycle is constant, so VCOMP is held constant. Under DCM, the VCOMP level is adjusted to obtain different duty cycles according to load condition. The VCOMP voltage shift in the DCM mode deteriorates the performance and introduces extra voltage deviation. Mode transitioning waveforms (between CCM and DCM) is shown in FIG. 2(a), while load transient waveforms are shown in FIG. 2(b).
FIG. 2(a) demonstrates that there exists significant VOUT deviation when the converter switches from the synchronous CCM operation at heavy load to DCM at light load, as well as from DCM at light load to CCM at heavy load. FIG. 2(b) demonstrates the load transient performance for VOUT at DCM (t3 to t5) is not be as good as at CCM (t0 to t2). What is needed is a controller circuit architecture or methodology to achieve the similar performance at both CCM and DCM conditions, and which limits voltage deviation when the converter switches between synchronous CCM operation at heavy load to DCM at light load.